Intel Foundry has become the first chipmaker on earth to ship high volume logic built with High NA EUV lithography, using machines that cost close to $400 million each. The yields match the previous generation of tools, which is the part nobody in the industry expected. For a company written off as a manufacturing laggard, this is the strongest evidence in years that the leading edge is back in play.
By Blumefield | July 19, 2026
The Milestone Nobody Expected Intel to Reach First
On July 15, ASML confirmed that Intel Foundry has entered high volume manufacturing on a subset of its Core Ultra Series 3 processors, code named Panther Lake, using High NA EUV lithography. It is the first time any chipmaker anywhere has shipped a high volume logic product patterned with the technology, and it happened in Oregon rather than in Hsinchu or Pyeongtaek.
The technical claim is narrow and worth stating precisely, because the loose version of it is already circulating and it is wrong. Specific layers of the Intel 18A process node are now dual qualified, which means the same layer can be exposed on either an existing 0.33 numerical aperture NXE scanner or the new 0.55 aperture EXE machine, and the resulting wafers are interchangeable. Product is going out to customers today. This is not a research demonstration or a hero wafer shown at a conference. It is inventory moving through a live supply chain.
The context sharpens it further. Intel took delivery of the industry's first commercial High NA EUV system in 2024 at its Hillsboro site, then became the first to install and pass acceptance testing on the second generation TWINSCAN EXE:5200B. Rivals watched, ordered cautiously, and waited for somebody else to pay for the learning curve. Intel paid for it. ASML's readiness milestone announcement uses the careful language of a supplier that does not want to overpromise, but the substance underneath is unambiguous.
Why Yield Parity Is the Entire Story
Strip away the physics and one number carries the announcement. ASML states that Intel is shipping the High NA EUV patterned product at yields matched to the NXE platform. Every previous lithography transition in the industry's history arrived with a yield penalty and a long, expensive climb out of it. Early EUV itself took the better part of a decade to reach economic parity with the immersion tools it replaced, and the companies that adopted it first spent years explaining depressed margins to shareholders.
Matched yields on first deployment breaks that pattern. It means the economic case for High NA EUV no longer depends on a promise about future learning. A fab manager can run the layer either way, on either tool, and the wafers come out the same. That optionality is worth more than the raw resolution gain in the short term, because it removes the single largest risk in adopting a tool that costs somewhere near $400 million and requires rebuilding a chunk of the fab around it.
There is an honest caveat, and Intel's own framing includes it. The company qualified a subset of layers on a subset of products. Nobody has yet run an entire advanced node exclusively on 0.55 aperture optics, and the hardest patterning problems sit in layers Intel has not publicly claimed. What has been proven is that the tool works in production at competitive economics on real layers of a real shipping processor. That is a materially different statement from the one the industry could make a year ago, and it is the statement that unlocks the next node.
ASML Books the Upside Immediately
The lithography monopoly published its Q2 results the same morning, and the juxtaposition was not accidental. ASML reported €9.3 billion in net sales, a 54.0 percent gross margin and €2.9 billion in net income, all above guidance. It then raised full year 2026 guidance to €43 billion to €45 billion in net sales at a 54 to 56 percent gross margin, up from a prior range of €36 billion to €40 billion at 51 to 53 percent. Guidance revisions of that magnitude are rare at any company and almost unheard of at one this large.
Chief executive Christophe Fouquet attributed the surge to AI related investment driving demand for advanced logic and memory. That is true but incomplete, and it understates what the High NA EUV result does to the order book. The Q2 filing reflects a business where the installed base management line, essentially service and upgrade revenue on tools already sold, is outperforming, and where the forward book is being reshaped by customers who now have proof that the next generation of EUV lithography systems works in production. Proof converts evaluation orders into fleet orders.
The commercial logic runs one direction only. ASML has no competitor at this node, so every chipmaker that concludes it cannot afford to be a generation behind on High NA EUV joins the same queue, at the same prices, on the same delivery schedule. Intel's milestone has effectively de risked the purchase decision for everyone else, which is an odd sort of gift for Intel to hand its rivals and a very good quarter for the company selling the machines.
What TSMC and Samsung Do Next
TSMC has been publicly relaxed about High NA EUV, arguing that multi patterning on existing 0.33 aperture tools remains more economical and that it would adopt the newer optics when the cost per wafer justified it. That position was defensible while nobody had demonstrated production yields. It is harder to hold now. TSMC posted a blowout quarter of its own this month and raised capital expenditure guidance sharply, so the money is plainly available. The question is whether the company wants to concede a first mover advantage in a capability it has never conceded before.
Samsung faces the sharper version of the same problem. Its foundry division has spent three years trying to convince customers that it can execute at the leading edge, and Intel just put High NA EUV into production while Samsung was still evaluating it. For a business competing on credibility rather than scale, being third to a manufacturing capability is expensive in ways that do not show up in a capex line.
For Intel the strategic value is specific and somewhat fragile. It does not win customers by itself. Foundry customers commit on the basis of yield, packaging, capacity and trust accumulated over multiple nodes, and Intel Foundry remains behind on most of those measures. What the milestone does is make the pitch for the forthcoming Intel 14A node credible in a way it was not in June. Naga Chandrasekaran, who runs Intel Foundry, framed the qualification as giving existing tools more output while the company develops the fuller capability for upcoming nodes. Read carefully, that is a sales document aimed at customers deciding where to place designs for 2028.
The Test That Still Sits Ahead
The gap between a qualified layer and a fully qualified node is where semiconductor roadmaps usually break. Intel has cleared the first, and the second is a substantially larger engineering problem involving overlay budgets, mask infrastructure, throughput at full utilisation and the field stitching constraints that come with the smaller exposure field of 0.55 aperture optics. None of those are solved by the announcement, and Intel has a long institutional history of announcing a lead and then losing it in execution.
What has changed is the direction of the burden of proof. For four years the sensible assumption about Intel manufacturing was that any claimed advantage would slip, and that assumption was usually correct. High NA EUV in volume production, at matched yields, shipping to paying customers, is the first piece of evidence in a long time that resists that reading. It is not a restoration of process leadership. It is the first credible argument in years that a restoration is possible.
The broader point for anyone tracking the AI buildout is that the constraint is migrating again. The industry spent 2025 obsessed with GPU supply, then with memory, then with power and interconnect. Lithography is the layer beneath all of them, and it now has exactly one supplier, a raised forecast, and a customer queue that just got a reason to lengthen. As Blumefield has argued through this cycle, the most consequential AI stories are increasingly the ones happening several layers below the models.