The memory hierarchy that powers artificial intelligence just gained a new layer. High Bandwidth Flash, unveiled as an open standard this week by Sandisk and SK hynix, is being positioned as the missing tier between fast, scarce memory and slow, cheap storage, and the industry is paying close attention.
By Blumefield | August 5, 2026
A New Rung on the Memory Ladder
For the past two years the memory industry has been defined by a single acronym, HBM, and a single problem, scarcity. On August 4, at the Future of Memory and Storage conference in Santa Clara, Sandisk and SK hynix tried to change that conversation. The two companies released the first standard specification for High Bandwidth Flash, a technology that slots a new rung into the memory ladder between costly High Bandwidth Memory and the ordinary solid state drives that fill data center racks.
The pitch is deceptively simple. The technology aims to deliver data transfer speeds in the same neighborhood as HBM while carrying far more capacity, because it is built on NAND flash rather than DRAM. NAND is cheaper per gigabyte and stacks higher, so a single device can hold vastly more of a large language model close to the processor. In an era when a frontier model's weights and context can run to hundreds of gigabytes, that proximity is the whole game.
Published through the Open Compute Project, the specification is deliberately open rather than proprietary. That framing matters. Sandisk and SK hynix are not selling a part yet. They are trying to establish High Bandwidth Flash as a shared blueprint that chip designers, cloud operators and rival memory makers can all build against before any single vendor locks in an advantage.
Why Inference Broke the Old Hierarchy
To understand why a new memory tier is even necessary, look at what has happened to the shape of AI workloads. Training built the reputation of HBM, and HBM in turn built the fortunes of SK hynix, Samsung and Micron. But the center of gravity has shifted to inference, the act of actually running models for millions of users, and inference has a different appetite that High Bandwidth Flash was designed to satisfy.
Serving a large model means holding enormous parameter sets and long context windows in memory that the accelerator can reach without stalling. Engineers call the resulting choke point the memory wall, the widening gap between how fast processors can compute and how fast they can be fed. HBM answers the bandwidth half of that equation beautifully, but it is capacity constrained and, thanks to insatiable AI demand, painfully expensive and supply limited. SSDs answer the capacity half cheaply, but they are far too slow to sit in the hot path of a running model.
High Bandwidth Flash is engineered for exactly that unhappy middle. Sandisk's chief technology officer, Alper Ilkbahar, framed the release around what he called token economics, the cost of generating each unit of AI output. "AI inference is creating a new set of memory requirements, and HBF technology is designed to meet that moment," he said, describing the specification as a practical path to bring high capacity memory closer to compute. When the marginal cost of a token determines whether an AI product makes money, a cheaper way to keep models resident near the processor is not a nicety. It is a business model.
Inside the Specification
The numbers give the concept teeth. The High Bandwidth Flash standard supports up to 512 gigabytes per device across two configurations, an 8 high and a 16 high stack of NAND dies. Bandwidth is sorted into three grades, scaling from roughly 0.4 terabytes per second at the entry level to 3.0 terabytes per second at the top. That upper figure lands within striking distance of current HBM, while the capacity dwarfs what a comparable HBM stack can hold.
Just as important is how the memory talks to the processor. The specification adopts UCIe, the Universal Chiplet Interconnect Express, an open interface for wiring heterogeneous chiplets together at high speed. Choosing UCIe rather than a bespoke link means High Bandwidth Flash can, in principle, be integrated across many kinds of accelerators and CPUs without every designer reinventing the plumbing. The document also codifies the unglamorous but essential details: electrical characteristics, reliability and packaging guidance for stacking the flash dies, and a software guide for read and write operations.
SK hynix reinforced the message with hardware. At its booth the company revealed a tenth generation, 375 layer 4D NAND wafer that it says improves performance per watt by 2.5 times over the prior generation, with mass production of high capacity enterprise SSDs based on it slated for early next year. Power efficiency is not a footnote here. Data centers are increasingly rationed by electricity, and a memory tier that moves more data per watt eases two constraints at once. You can read SK hynix's full account of the launch in its own newsroom announcement.
Google, Tenstorrent and the Open Standard Play
A specification is only as strong as the coalition behind it, and this is where the announcement gets strategically interesting. The High Bandwidth Flash workstream began under the Open Compute Project in February, just six months before the spec landed, following an initial partnership between Sandisk and SK hynix struck in August 2025. During that window two heavyweight names joined as consortium members: Google and Tenstorrent, the AI chip firm led by veteran silicon architect Jim Keller.
Their participation is a signal to the rest of the industry. Google operates one of the largest fleets of custom AI accelerators on earth, and its DeepMind engineers are slated to sit on the conference panel bluntly titled "Breaking the Memory Wall with High Bandwidth Flash." When a hyperscaler of that scale helps validate a memory standard before it ships, it tells competitors and customers alike that real demand is being modeled, not merely imagined. Sandisk detailed the consortium's makeup and goals in its press release accompanying the launch.
The open approach is also a calculated bet against fragmentation. By publishing through the Open Compute Project, the two companies are trying to make High Bandwidth Flash the de facto standard early, fostering an ecosystem of tools, packaging partners and accelerator designs rather than a walled garden. In memory markets, standards win. The history of DRAM, NAND and HBM itself shows that the format everyone can build against tends to beat the technically elegant part that only one supplier makes.
What It Means for the AI Buildout
For all the ambition, the framing is notably measured. Neither company is claiming High Bandwidth Flash will replace HBM. The specification is explicitly designed so the two can coexist in the same system, HBM handling the most bandwidth hungry tasks while the flash tier holds the larger pool of near compute data. SK hynix wrapped the idea in the language of tiered memory, arguing that no single memory type can serve the agentic AI era where autonomous systems generate and consume data at punishing rates. As executive vice president Kim Chun-sung put it, the industry is "at a point where overall data processing structures must be redesigned."
That redesign, if it takes hold, reshapes the competitive map. A viable High Bandwidth Flash tier could relieve some of the desperate pressure on HBM supply that has enriched the memory makers and squeezed every buyer of AI hardware. It could lower the cost of serving large models, which matters to every company trying to turn AI features into profit rather than a subsidy. And it hands NAND, long treated as the commodity basement of the memory business, a credible claim to a premium seat at the AI table.
The caveats are real. A specification is not a shipping product, ecosystems take years to mature, and flash carries endurance and latency tradeoffs that DRAM does not. High Bandwidth Flash will have to prove itself in real inference systems before the promise becomes revenue. But the memory wall is not a theoretical problem, and it is not going away as models grow. For a deeper look at how the AI infrastructure race keeps colliding with physical limits, see our ongoing coverage at Blumefield. The contest to feed the machines is now every bit as fierce as the contest to build them.